We generally associate the Power Distribution Network (“PDN”) with the power circuits used to drive CPUs and FPGAs. The increasing use of FPGAs in our products certainly means that at some point we will all need to be fluent in PDN. In reality, PDN applies to all circuits and not just FPGAs and CPUs. Even everyday glue logic, such as high speed CMOS gates can wreak havoc in a PDN. The ultimate results of poor PDN design range from non-functional circuits in cases where the PDN fails to maintain adequate voltage regulation to the high speed circuit, to noisy circuits, where the PDN noise flows through the system through various distribution paths, such as PCB crosstalk or regulator PSRR. While understanding and optimization your PDN can require a great deal of effort, including expensive 3D simulations, the fundamental concepts can be simply stated in five key points.
Keep it flat
Most PDN books tell you that the best performing PDN impedance looks flat over frequency. That is because noise signals are generated as a result of discontinuities or impedance peaks in the PDN. The PDN is comprised of resistance, inductance and capacitance associated with the PCB traces and planes, the decoupling capacitors and their parasitics and the package parasitics including the bond wires and die capacitance of the high speed devices. Minimizing the Q of these resonant circuits is the key to obtaining a flat impedance. One of the fundamental PDN management tools is target impedance. This is the impedance below which all peaks should be maintained for good performance. The target impedance concept may have significant flaws [1], but it is still the most common PDN design technique in use today. However, the more basic goal should be to maintain the impedance as flat as possible up to a bandwidth that is dependent on the edge speed of the load signals, the amplitude of the dynamic current change and the impedance of the PDN. Note that this is the edge speed and not the pulse repetition frequency dependent.
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