Figure 1 Schematic of the logic gate buffer circuit, which converts the high output impedance, 10MHz clock to a 50? output.When we think of a power distribution network (PDN), the first images that usually come to mind are FPGAs and CPUs. These circuits generally require ultra-low PDN impedance in order to maintain the appropriate voltage at the FPGA or CPU during the large dynamic current variations these devices present. This study focuses on a much smaller scale, addressing a very simple circuit that experiences related PDN issues. While the issues shown here may seem obvious to some, this is an excellent example of a very common problem.


A single tiny logic gate

The first case we’ll look at is a Fairchild NC7SZ04 ultra-high-speed inverter gate. This logic gate is a single inverter gate in an SOT-23 package, and it is part of a Picotest demonstration board designed to illustrate a PDN issue in a very simple low-power circuit (see Figure 1). The inverter gate is used as a buffer between a 10MHz clock and a 50 Ohm port. The output impedance of the logic gate is approximately 20 Ohms, and R20 adds an additional 30 Ohms to total 50 Ohms in order to match the coaxial cable and input terminator on the oscilloscope. Resistor R18 is a 0805 package film resistor, which was increased from 0.2 Ohms (see Figure 2) to 1 Ohms in the tests here to make the device current signal easier to see, so the scaling is 1V/A. This resistor does contribute to the issue, but it is not the dominant term.

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