Power Integrity Using ADS
Synopsis
The need for Power Distribution Network (PDN) simulation is essential due to its impact on power rail compliance, signal integrity, and electro-magnetic interference (EMI). Evolutionary increases in data rates and edge speeds, coincident with decreasing power rail voltages put ever more pressure on power integrity and system engineers to maintain optimum system performance.
Power integrity assurance requires end-to-end simulation including analog and power electronics, as well as, power-aware signal integrity simulation. This also includes details, such as control loop assessment, capacitor and inductor modeling, and DC IR drop including remote sense lines and Printed Circuit Board (PCB) effects.
Keysight Technologies’ Pathwave Advanced Design System (ADS), the world’s leading Electronic Design Automation (EDA) software package, addresses analog, RF, microwave, high speed digital and power electronics applications, including PCB effects, in a single simulation environment.
Pathwave ADS provides this much needed end-to-end capability including large signal, non-linear Harmonic Balance (HB) simulation. The ADS Harmonic Balance simulator provides ultra-fast time domain and spectral content of switching power supply waveforms and power rail noise without the long simulation times or convergence issues typically associated with transient simulation.
In “Power Integrity Using ADS”, award-winning, internationally recognized power integrity guru, and Keysight Certified EDA expert, Steven M. Sandler and Anto K. Davis, share their simulation experience and workspaces to provide a quick and easy guide to best Power Integrity design practices and simulation techniques.
Chapter 1 – An Introduction to ADS
Keysight Technologies’ PathWave® Advanced Design System (‘ADS’) provides a modular simulator environment for practical power integrity studies. This chapter is for those who are not familiar with ADS to get started on the basics. It contains only the basic features necessary for power integrity analysis used in this book. Sample Workspaces are provided.
Chapter 2
How to Design for Power Integrity: Finding Power Delivery Noise Problems, June, 2015
This video provides an understanding of how the voltage regulator module (VRM) interacts with the printed circuit board planes and decoupling capacitors within a power distribution network (PDN). A well designed PDN provides optimum system performance while a poorly matched designed PDN can result in poor system performance. In the extreme case, rogue waves can occur within the PDN generating much higher voltage noise levels than expected, potentially interfering with system performance or resulting in permanent damage. Recommendations for keeping the impedance flat are also provided.
Chapter 3 & 4
How to Design for Power Integrity: Measuring, Modeling, Simulating Capacitors and Inductors, November, 2016
Power supply switching ripple and control loop phase margin are dominated by the output inductor and the bulk capacitors. Simple RLC capacitor and inductor models can result in a design with more capacitors than necessary adding to the design cost, consuming valuable circuit board real estate and degrading the control loop performance. Most capacitor datasheets provide very limited information, such as maximum ESR at 100kHz and not the desired information regarding typical values and frequency dependencies of the C, ESR, and ESL. This short video will show how to make these measurements efficiently and how to use the results directly or create high fidelity measurement based models for simulation in ADS.
Chapter 5
How to Design for Power Integrity: Selecting a VRM, May 5, 2016
Many signal and power integrity issues are the result of poor VRM selection. This critical selection is often made arbitrarily due to insufficient, incomplete or incorrect data. Costly design time and multiple board spins can be minimized by following a few simple guidelines and performing a few simple simulations and measurements early in the process. This video explains why one should avoid Voltage mode VRMs and shunt compensation for the VRM Error Amplifier. The better performance of a current mode VRM with series compensation for the Error Amplifier is clearly demonstrated with simulations and measurements.
Chapter 6 & 7
How to Design for Power Integrity: DC-DC Converter Modeling and Simulation, April 7, 2017
Creating a model from a datasheet isn’t an option since much of the data required isn’t published. Fortunately, a measurement based model (MBM) can easily be developed using just a few, simple measurements. The model supports AC, DC, Transient, HB and EM simulations allowing fast, real-time optimization of the VRM design. 1. The LM25116 with Voltage Amp Feedback (a buffered OTA) 2. The Simple LM20143 with Output Transconductance Amplifier (OTA) Feedback 3. Multiphase Operation with the TPS40140 4. Building the Power Integrity Eco-System with VRM and PDN Models.
Chapter 8
How to Design for Power Integrity: Optimizing Decoupling Capacitors, June, 2018
Learn how to optimize decoupling capacitors for the best cost vs. performance using flat target impedance design methods. Impedance peaks caused by parallel L-C resonances in the power distribution network (PDN) are potential sources of power rail ripple and increased EMI. Bulk capacitors must be selected to ensure power supply stability while high frequency decoupling must insure the required bandwidth at the Load. Simple SPICE simulations fail to account for PCB parasitics and often result in the wrong selection of decoupling capacitors. Utilizing EM models of the PDN and combining them with power supply state space average models and the spectral requirements of the load result in good agreement with measurements. Optimizing this PDN ecosystem shows that designing for flat impedance is the best way to achieve the lowest noise on the power rail with the minimum number of capacitors.
Chapter 2
This simulation workspace utilizes schematic driven time domain simulations to design low noise power delivery networks (PDN). The design starts with a simple model of a power delivery network to verify the expected natural step response, forced sinusoidal and square wave responses. The model complexity is increased to add multiple resonances to represent the voltage regulator module (VRM), the PCB inductance with bulk capacitors, and the ceramic decoupling capacitors. An optimizer is then used to search for the maximum voltage noise or rogue wave excursion that can exist with the multiple resonances and a forced digital load pattern from a real world PDN.
Chapter 3
- How low fidelity RLC capacitor models over estimate the number of capacitors needed to reduce PDN ripple.
- How high fidelity models are measured with the 2-port shunt through method to give the best dynamic range for the data
- How to use measured data to create a high fidelity multi-element lumped model using tuning and an optimizer.
Chapter 4
The Workspace contains two folders – “01_InductorModeling” and “02_FerriteBeadsModeling.” Both the inductor and ferrite bead models use measured data to obtain the parameters. Sample measured data is available inside the folders “…\AEM_FERRITE_BEADS_wrkndatanInductorMeasuredDatan” and “…\AEM_FERRITE_BEADS_wrkndatanFerriteBeadsMeasuredDatan” Refer to [5, chapter7] for high-fidelity DC biased measurements. The ADS Optimizer is used to tunethe model parameters. A component (inductor or ferrite bead) model can be createdwith its measurement data and the procedure is explained in this chapter.
Chapter 5
The workspace follows along with the examples in the video and has the following sections:
- A VRM Reference Design vs an Improved VRM Design that shows the goal of this workspace.
- Why it is important to have a flat PDN impedance design for the VRM
- A Voltage Mode vs Current Mode VRM simulation using state based averaged models
- VRM Error Amp Feedback Design: Shunt vs Series
- Exploring the impact of worst case fabrication tolerances on Voltage Mode vs Current Mode
- Combining a State-Based Average VRM model with a Switch Mode transient model for design exploration.
Chapter 6 & 7
This workspace is used by Chapter 6 and Chapter 7. The state space models explained in this workspace are based on measurement results. The power integrity eco-system can be built with the measurement based models by including the PCB layout effects. The Workspace contains the following topics,
- The LM25116 with Voltage Amp Feedback (a buffered OTA)
- The Simple LM20143 with Output Transconductance Amplifier (OTA) Feedback
- Multiphase Operation with the TPS40140
- Building the Power Integrity Eco-System with VRM and PDN Models
Chapter 8
This workspace is used by Chapter 9 and Chapter 8. The decouplingcapacitor optimizations explained in this workspace are required to obtain a flatimpedance profile which is essential for power integrity. The Workspace contains thefollowing topics,
- Parallel LC resonances
- Calculating C value for flat impedance profile
- Adding PCB parasitics using the layout file in PIPro for EM simulations
- Conventional capacitor selection methods for a PDN
- DDR4 decoupling capacitor optimization
Appendix A
This Workspace studies various cases of antiresonant peak formation when two capacitors are connected in parallel. It has the following sections:
- Three Cases of Antiresonances
- LC Tank Circuit
- Equal Capacitors with Positive and Negative Coupling
- Different Capacitors with Positive and Negative Coupling
- Critical Damping of Two Capacitors
Appendix B
The workspace contains one schematic for studying the effect of ground loop on 2-port shunt-through impedance measurements and how the common mode transformer breaks this loop. The transformer coupling coefficient T=1 breaks the ground loop. The condition T=0 is equivalent to NOT having a transformer in the loop. The Zg is the impedance of the ground loop. The IEC safety standard allows you to have a maximum of 50? in the ground loop which is utilized by some VNAs to break the ground loop. However, this is less effective than having a ground loop breaking common mode transformer or a solid state ground loop breaker. The Zg can be 1nH+0.1m?(represents a small impedance) or 1nH+50m?(allowed maximum impedance through IEC standards). The 1nH represents that the two ports of the VNAs are physically separated and will have a small inductance of the connection.
Appendix C
This Workspace explains with example what the die/chip sees as impedance looking into the PDN. This impedance is not same as the transfer impedance between VRM and the die/chip. The 2-port shunt-through impedance configuration is used to measure ultra-low impedance(m?s and lower) in power integrity measurements. Its connection geometry is such that both the ports are connected to the same point. The differences between the different type of port connections are explained with examples in this Workspace.